Project Code | Project Title |
---|---|
VLSI2017001 | A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm |
VLSI2018001 | Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA |
VLSI2018002 | Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding |
VLSI2018003 | Register Less NULL convention logic |
VLSI2018004 | RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing |
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